A Verilog-AMS description of a mixed-signal circuit design includes semantics of initialization and time-sweep phases of a transient analysis for a simulation cycle of the circuit design. A VHDL-AMS description of the mixed-signal circuit provides a conceptual representation of a simulation cycle for the relative sequencing of analog execution, digital signal updates, digital process execution, postponed process execution, DOMAIN signal changes, initialization, delta cycle behavior, and BREAK set processing.
The differences in the representation of a simulation cycle may prevent the two languages from being used together in a simulation. For example, in a simulation cycle, the relative sequencing of processes performed in VHDL may not be synchronized with the phases of the analysis which are performed in Verilog, because VHDL processes analog to digital events during a BREAK, while Verilog does not BREAK a digital simulation in response to an analog to digital event.
Therefore, the simulation performance and accuracy for the mixed-signal circuit may be adversely affected by the differences in the two languages.